목록Wireless Comm./VHDL (36)

UOMOP

Serial to Parallel using VHDL

RTL code library ieee; use ieee.std_logic_1164.all; entity Serial2Parallel is port( nrst : in std_logic; sclk : in std_logic; pclk : in std_logic; inbit : in std_logic; outbits : out std_logic_vector(1 downto 0) ); end Serial2Parallel; architecture arch of Serial2Parallel is signal inbuf : std_logic; begin process(nrst, sclk) begin if nrst = '0' then inbuf mclk, clk8x => clk8x, clk4x => clk4x, c..
Wireless Comm./VHDL 2022. 4. 26. 17:03
Parallel to Serial using VHDL

RTL code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Parallel2Series is port(nrst : in std_logic; sclk : in std_logic; inbits : in std_logic_vector(1 downto 0); sel : in std_logic_vector(0 downto 0); finalbit : out std_logic ); end Parallel2Series; architecture arch of Parallel2Series is begin process(nrst, sclk) begin if nrst = '0' then finalbit
Wireless Comm./VHDL 2022. 4. 26. 17:01
Clock Generator using VHDL

Module Source Code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clkgen is port( nrst, mclk : in std_logic; clk8x, clk4x, clk2x, clk1x : out std_logic); end clkgen; architecture func of clkgen is signal x8, x4, x2, x1 : std_logic; signal output : std_logic_vector(3 downto 0); begin process(nrst, mclk) begin if nrst = '0' then output '0'); x8
Wireless Comm./VHDL 2022. 3. 22. 20:00
Random Bit Generator using VHDL

Module Source Code library ieee; use ieee.std_logic_1164.all; entity rbgen is port (nrst, clk : in std_logic; outbit : out std_logic); end rbgen; architecture func of rbgen is signal d : std_logic_vector(11 downto 0); signal fb : std_logic; begin fb
Wireless Comm./VHDL 2022. 3. 22. 19:57
Latched Adder using VHDL

Module Source Code library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity latchedadder is port( nrst, clk : in std_logic; InData : in std_logic_vector(7 downto 0); OutData : out std_logic_vector(7 downto 0)); end latchedadder; architecture behavior of latchedadder is signal b, a : std_logic_vector(7 downto 0); begin process(nrst, clk) begin if nrst = '0' then b '0'); ..
Wireless Comm./VHDL 2022. 3. 22. 19:54
Up/Down 4bits counter using ModelSim

Module Source Code library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity up_down_counter is port( nrst : in std_logic; clk : in std_logic; sel : in std_logic; cntout : out std_logic_vector(3 downto 0)); end up_down_counter; architecture behavior of up_down_counter is signal cnt : std_logic_vector(3 downto 0); begin process(nrst, clk, sel) begin if nrst = '0' then cnt..
Wireless Comm./VHDL 2022. 3. 22. 19:52
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