Parallel to Serial using VHDL

RTL code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Parallel2Series is

port(	nrst   : in std_logic;
	sclk   : in std_logic;
	inbits : in std_logic_vector(1 downto 0);
	sel    : in std_logic_vector(0 downto 0);

	finalbit : out std_logic
	);

end Parallel2Series;

architecture arch of Parallel2Series is
begin
	process(nrst, sclk)
	begin
		if nrst = '0' then
			finalbit <= '0';
		elsif sclk'event and sclk = '1' then
			if sel = "0" then
				finalbit <= inbits(1);
			else
				finalbit <= inbits(0);
			end if;
		end if;
	end process;
end arch;

---

Testbench code

library ieee;
use ieee.std_logic_1164.all;

entity tb_Parallel2Series is
end tb_Parallel2Series;

architecture behavior of tb_Parallel2Series is

component clkgen
   port(nrst  : in std_logic;
        mclk  : in std_logic;
   
        clk8x : out std_logic;   
        clk4x : out std_logic;
        clk2x : out std_logic;
        clk1x : out std_logic
   );
end component;

component rbgen
   port(nrst : in std_logic;
        clk  : in std_logic;

        rbit : out std_logic
   );
end component;

component Serial2Parallel
   port(nrst  : in std_logic;
        sclk  : in std_logic;
        pclk  : in std_logic;
        inbit : in std_logic;

        outbits : out std_logic_vector(1 downto 0)
   );
end component;

component Parallel2Series
	port(	nrst   : in std_logic;
		sclk   : in std_logic;
		inbits : in std_logic_vector(1 downto 0);
		sel    : in std_logic_vector(0 downto 0);

		finalbit : out std_logic
	);
end component;

component onebitcounter
	port(	nrst : in std_logic;
		sclk : in std_logic;

		cntout : out std_logic_vector(0 downto 0)
	);
end component;


signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;
signal rbit : std_logic;
signal outbits : std_logic_vector(1 downto 0);
signal state : std_logic_vector(0 downto 0);
signal finalbit : std_logic;


begin 
iclkgen : clkgen port map(
      nrst  => nrst, 
      mclk  => mclk,
      clk8x => clk8x, 
      clk4x => clk4x,
      clk2x => clk2x,
      clk1x => clk1x
   );

irbgen : rbgen port map(
      nrst => nrst, 
      clk  => clk2x,
      rbit => rbit
   );

is2p : Serial2Parallel port map(
      nrst    => nrst, 
      sclk    => clk2x,
      pclk    => clk1x,
      inbit   => rbit,
      outbits => outbits
   );

icnt : onebitcounter port map(
	nrst => nrst,
	sclk => clk2x,
	cntout => state
	);

ip2s : Parallel2Series port map(
	nrst => nrst,
	sclk => clk2x,
	sel => state,
	inbits => outbits,
	finalbit => finalbit
	);

tb : process
begin
   mclk <= '1';
   wait for 20 ns;
   mclk <= '0';
   wait for 20 ns;
end process;

rstp : process
begin
   nrst <= '0';
   wait for 100 ns;
   nrst <= '1';
   wait;
end process;

end behavior;

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