목록Wireless Comm./VHDL (36)

UOMOP

Final

RTL(QPSK_PED) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; use ieee.std_logic_arith.all; library work; use work.mypackage.all; entity QPSK_PED is port( nrst : in std_logic; clk : in std_logic; rin, iin : in std_logic_vector(9 downto 0); Perr : out std_logic_vector(9 downto 0)); end entity; architecture arch of QPSK_PED is signal Rsign, Isign : std_logic; begin Rsign ..
Wireless Comm./VHDL 2022. 7. 12. 22:45
Whole Processing using DQPSK

TestBench code library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mypackage.all; entity tb_whole_14week is end entity; architecture behavior of tb_whole_14week is component rbgen is port( nrst, clk : in std_logic; rbit : out std_logic); end component; component clkgen is port( nrst, mclk : in std_logic; clk8x, clk4x, clk2x, clk1x : out std_logic); end com..
Wireless Comm./VHDL 2022. 7. 11. 22:41
DQPSK DeMapper

RTL code library ieee; use ieee.std_logic_1164.all; entity DQPSKdemapper is port( nrst, clk : in std_logic; rdata, idata : in std_logic_vector(5 downto 0); outbits : out std_logic_vector(1 downto 0)); end entity; architecture arch of DQPSKdemapper is component QAM4demapper is port( nrst, sclk : in std_logic; rdata, idata : in std_logic_vector(5 downto 0); outbits : out std_logic_vector(1 downto ..
Wireless Comm./VHDL 2022. 7. 10. 22:39
DQPSK Mapper

RTL code library ieee; use ieee.std_logic_1164.all; entity DQPSKmapper is port( nrst, clk : in std_logic; cdata : in std_logic_vector(1 downto 0); rout, iout: out std_logic_vector(5 downto 0)); end entity; architecture arch of DQPSKmapper is component QAM4mapper is port( nrst, sclk : in std_logic; inbits : in std_logic_vector(1 downto 0); rdata : out std_logic_vector(5 downto 0); idata : out std..
Wireless Comm./VHDL 2022. 7. 8. 22:37
Whole Processing using PhaseSplitter

TestBench code library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mypackage.all; entity whole_12week is end entity; architecture behavior of whole_12week is component rbgen is port( nrst, clk : in std_logic; rbit : out std_logic); end component; component clkgen is port( nrst, mclk : in std_logic; clk8x, clk4x, clk2x, clk1x : out std_logic); end component..
Wireless Comm./VHDL 2022. 7. 7. 22:34
Compare_PhaseSplit

TestBench library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mypackage.all; entity compare_PhaseSplit is end entity; architecture behavior of compare_PhaseSplit is component rbgen is port( nrst, clk : in std_logic; rbit : out std_logic); end component; component clkgen is port( nrst, mclk : in std_logic; clk8x, clk4x, clk2x, clk1x : out std_logic); end co..
Wireless Comm./VHDL 2022. 7. 6. 22:31
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