Clock Generator using VHDL

Module Source Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clkgen is
   port( nrst, mclk                 : in std_logic;
         clk8x, clk4x, clk2x, clk1x : out std_logic);
end clkgen;

architecture func of clkgen is
   signal x8, x4, x2, x1 : std_logic;
   signal output : std_logic_vector(3 downto 0);

begin
   process(nrst, mclk)
   begin
      if nrst = '0' then
         output <= (others => '0');
         x8 <= '0';
         x4 <= '0';
         x2 <= '0';
         x1 <= '0';
      elsif mclk = '1' and mclk'event then
         output <= output + 1;
            if output(0) = '1' then
               x8 <= '1';
            else
               x8 <= '0';
            end if;
            if output(1) = '1' then
               x4 <= '1';
            else
               x4 <= '0';
            end if;
            if output(2) = '1' then
               x2 <= '1';
            else 
               x2 <= '0';
            end if;
            if output(3) = '1' then
               x1 <= '1';
            else
               x1 <= '0';
            end if;
      end if;
   end process;
      clk8x <= x8;
      clk4x <= x4;
      clk2x <= x2;
      clk1x <= x1;

end func;

---

Testbench Source Code

library ieee;
use ieee.std_logic_1164.all;

entity tb_clkgen is
end tb_clkgen;

architecture behavior of tb_clkgen is

component clkgen port(
   nrst, mclk : in std_logic;
   clk8x, clk4x, clk2x, clk1x : out std_logic);
end component;

signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;

begin
   iclkgen : clkgen port map(
      nrst => nrst,
      mclk  => mclk,
      clk8x => clk8x,
      clk4x => clk4x,
      clk2x => clk2x,
      clk1x => clk1x   );

   pmclk : process
   begin
      mclk <= '1';
      wait for 20 ns;
      mclk <= '0';
      wait for 20 ns;
   end process;

   pnrst : process
   begin
      nrst <= '0';
      wait for 100 ns;
      nrst <= '1';
      wait;
   end process;

end behavior;

---