Random Bit Generator using VHDL

Module Source Code

library ieee;
use ieee.std_logic_1164.all;

entity rbgen is
	port (nrst, clk : in std_logic;
	      outbit    : out std_logic);
end rbgen;

architecture func of rbgen is

	signal d  : std_logic_vector(11 downto 0);
	signal fb : std_logic;


	begin
		fb <=(d(5)xor(d(7)xor(d(10)xor d(11))));

	    process(nrst, clk)
		variable i : std_logic;
	    begin

		if nrst = '0' then
			d <= "100000100101";   
		elsif clk = '1' and clk'event then
			d(0) <= fb;
			for i in 1 to 11 loop
				d(i) <= d(i-1);
			end loop;
		end if;
	    end process;

		outbit <= d(11);


end func;

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Testbench Source Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_rbgen is
end tb_rbgen;
architecture behavior of tb_rbgen is
	component rbgen
		port( nrst, clk : in std_logic;
		      outbit    : out std_logic);
	end component;
	signal nrst, clk, rbit : std_logic;
begin
	irbgen : rbgen port map(
			nrst   => nrst,
			clk    => clk,
			outbit => rbit);
	info_clk : process
		begin
			clk <= '1';
			wait for 20 ns;
			clk <= '0';
			wait for 20 ns;
	end process;

	info_nrst : process
		begin
			nrst <= '0';
			wait for 100 ns;
			nrst <= '1';
			wait;
	end process;
end;

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