Serial to Parallel using VHDL

RTL code

library ieee;
use ieee.std_logic_1164.all;

entity Serial2Parallel is

port(   nrst    : in std_logic;
   sclk    : in std_logic;
   pclk    : in std_logic;
   inbit   : in std_logic;
   outbits : out std_logic_vector(1 downto 0)
);

end Serial2Parallel;



architecture arch of Serial2Parallel is
signal inbuf : std_logic;

begin

   process(nrst, sclk)
   begin
      if nrst = '0' then
         inbuf <= '0';
      elsif sclk'event and sclk = '1' then
         inbuf <= inbit;
      end if;
   end process;

   
   process(nrst, pclk)
   begin
      if nrst = '0' then
         outbits <= (others => '0');
      elsif pclk'event and pclk = '1' then
         outbits <= inbuf & inbit;     
      end if;
   end process;

end arch;

---

Testbench code

library ieee;
use ieee.std_logic_1164.all;

entity tb_Serial2Parallel is
end tb_Serial2Parallel;

architecture behavior of tb_Serial2Parallel is

component clkgen
   port(nrst  : in std_logic;
        mclk  : in std_logic;
   
        clk8x : out std_logic;   
        clk4x : out std_logic;
        clk2x : out std_logic;
        clk1x : out std_logic
   );
end component;

component rbgen
   port(nrst : in std_logic;
        clk  : in std_logic;

        rbit : out std_logic
   );
end component;

component Serial2Parallel
   port(nrst  : in std_logic;
        sclk  : in std_logic;
        pclk  : in std_logic;
        inbit : in std_logic;

        outbits : out std_logic_vector(1 downto 0)
   );
end component;

signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;
signal rbit : std_logic;

signal outbits : std_logic_vector(1 downto 0);


begin 
iclkgen : clkgen port map(
      nrst  => nrst, 
      mclk  => mclk,
      clk8x => clk8x, 
      clk4x => clk4x,
      clk2x => clk2x,
      clk1x => clk1x
   );

irbgen : rbgen port map(
      nrst => nrst, 
      clk  => clk2x,
      rbit => rbit
   );

is2p : Serial2Parallel port map(
      nrst    => nrst, 
      sclk    => clk2x,
      pclk    => clk1x,
      inbit   => rbit,
      outbits => outbits
   );

tb : process
begin
   mclk <= '1';
   wait for 20 ns;
   mclk <= '0';
   wait for 20 ns;
end process;

rstp : process
begin
   nrst <= '0';
   wait for 100 ns;
   nrst <= '1';
   wait;
end process;

end behavior;

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