UOMOP

RLT code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; library work; use work.mypackage.all; entity PhaseSplitter is port( nrst, clk : in std_logic; PS_Iin : in std_logic_vector(9 downto 0); PS_Iout, PS_Qout : out std_logic_vector(9 downto 0)); end entity; architecture arch of PhaseSplitter is signal reg : std_10b_array(14 downto 0); sign..

RTL(CPX_mul) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use work.mypackage.all; entity CPX_mul is port( nrst, clk : in std_logic; base_r, base_i : in std_logic_vector( 9 downto 0 ); NCO_r, NCO_i : in std_logic_vector( 9 downto 0 ); pass_r, pass_i : out std_logic_vector(9 downto 0)); end entity; architecture arch of CPX_mul is signal ba..

RTL code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library work; use work.NCO_ROM_package.all; entity NCO is port( nrst, clk : in std_logic; omega : in std_logic_vector(7 downto 0); NCO_I, NCO_Q : out std_logic_vector(9 downto 0)); end entity; architecture arch of NCO is signal omega_in, omega_add, omega_added, omega_delay : std_log..

NCO_ROM_package library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; package NCO_ROM_package is constant NCOROM_Address : integer := 2**8; constant NCOROM_Data : integer := 10; type ROM_TYPE is array(0 to NCOROM_Address - 1) of std_logic_vector(NCOROM_Data - 1 downto 0); constant COSROM_TABLE : ROM_TYPE := ROM_TYPE '( conv_std_logic_vector( 511 ..

TestBench code library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mypackage.all; entity tb_whole_until_conv is end entity; architecture behavior of tb_whole_until_conv is component rbgen is port( nrst, clk : in std_logic; rbit : out std_logic); end component; component clkgen is port( nrst, mclk : in std_logic; clk8x, clk4x, clk2x, clk1x : out std_logic);..

RTL code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity downconv is port( clk, nrst : in std_logic; pass_r, pass_i : in std_logic_vector(9 downto 0); base_r, base_i : out std_logic_vector(9 downto 0)); end entity; architecture arch of downconv is signal p_r, p_i, n_r, n_i : std_logic_vector(9 downto 0); signal basing_r, basing_i : s..