CPX_mul

RTL(CPX_mul)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.mypackage.all;

entity CPX_mul is
port(
	nrst, clk      : in std_logic;
	base_r, base_i : in std_logic_vector( 9 downto 0 );
	NCO_r, NCO_i   : in std_logic_vector( 9 downto 0 );

	pass_r, pass_i : out std_logic_vector(9 downto 0));
end entity;

architecture arch of CPX_mul is

signal base_r_sig, base_i_sig, nco_r_sig, nco_i_sig : std_logic_vector(9 downto 0);
signal base_r_nco_r, base_i_nco_i, base_i_nco_r, base_r_nco_i : std_logic_vector(19 downto 0);
signal after_add_r, after_add_i : std_logic_vector(20 downto 0);
signal after_sat_r, after_sat_i : std_logic_vector(9 downto 0);

begin

base_r_nco_r <= base_r_sig * nco_r_sig;
base_i_nco_i <= base_i_sig * nco_i_sig;
base_i_nco_r <= base_i_sig * nco_r_sig;
base_r_nco_i <= base_r_sig * nco_i_sig;

after_add_r <= sxt(base_r_nco_r, 21) - sxt(base_i_nco_i, 21);
after_add_i <= sxt(base_i_nco_r, 21) + sxt(base_r_nco_i, 21);

after_sat_r <= rndsat( after_add_r, 9, 2 );
after_sat_i <= rndsat( after_add_i, 9, 2 );

process(nrst, clk)
begin
if nrst = '0' then
	base_r_sig <= (others => '0');
	base_i_sig <= (others => '0');
	nco_r_sig  <= (others => '0');
	nco_i_sig  <= (others => '0');
elsif clk = '1' and clk'event then
	base_r_sig <= base_r;
	base_i_sig <= base_i;
	nco_r_sig  <= nco_r;
	nco_i_sig  <= nco_i;
end if;
end process;

process(nrst, clk)
begin
if nrst = '0' then
	pass_r <= (others => '0');
	pass_i <= (others => '0');
elsif clk = '1' and clk'event then
	pass_r <= after_sat_r;
	pass_i <= after_sat_i;
end if;
end process;

end arch;

---

RTL(CPX_mul_comp)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.mypackage.all;

entity CPX_comp_mul is
port(
	nrst, clk      : in std_logic;
	pass_r, pass_i : in std_logic_vector( 9 downto 0 );
	NCO_r, NCO_i   : in std_logic_vector( 9 downto 0 );

	base_r, base_i : out std_logic_vector(9 downto 0));
end entity;

architecture arch of CPX_comp_mul is

signal pass_r_sig, pass_i_sig, nco_r_sig, nco_i_sig : std_logic_vector(9 downto 0);
signal pass_r_nco_r, pass_i_nco_i, pass_i_nco_r, pass_r_nco_i : std_logic_vector(19 downto 0);
signal after_add_r, after_add_i : std_logic_vector(20 downto 0);
signal after_sat_r, after_sat_i : std_logic_vector(9 downto 0);

begin

pass_r_nco_r <= pass_r_sig * nco_r_sig;
pass_i_nco_i <= pass_i_sig * nco_i_sig;
pass_i_nco_r <= pass_i_sig * nco_r_sig;
pass_r_nco_i <= pass_r_sig * nco_i_sig;

after_add_r <= sxt(pass_r_nco_r, 21) + sxt(pass_i_nco_i, 21);
after_add_i <= sxt(pass_i_nco_r, 21) - sxt(pass_r_nco_i, 21);

after_sat_r <= rndsat( after_add_r, 9, 2 );
after_sat_i <= rndsat( after_add_i, 9, 2 );

process(nrst, clk)
begin
if nrst = '0' then
	pass_r_sig <= (others => '0');
	pass_i_sig <= (others => '0');
	nco_r_sig  <= (others => '0');
	nco_i_sig  <= (others => '0');
elsif clk = '1' and clk'event then
	pass_r_sig <= pass_r;
	pass_i_sig <= pass_i;
	nco_r_sig  <= nco_r;
	nco_i_sig  <= nco_i;
end if;
end process;

process(nrst, clk)
begin
if nrst = '0' then
	base_r <= (others => '0');
	base_i <= (others => '0');
elsif clk = '1' and clk'event then
	base_r <= after_sat_r;
	base_i <= after_sat_i;
end if;
end process;

end arch;