NCO

RTL code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.NCO_ROM_package.all;

entity NCO is
port(
	nrst, clk    : in std_logic;
	omega        : in std_logic_vector(7 downto 0);
	NCO_I, NCO_Q : out std_logic_vector(9 downto 0));
end entity;

architecture arch of NCO is

signal omega_in, omega_add, omega_added, omega_delay : std_logic_vector(7 downto 0);
signal sdata, cdata : std_logic_vector(9 downto 0);

begin

process(nrst, clk)
begin

if nrst = '0' then
	omega_delay <= (others => '0');
elsif clk = '1' and clk'event then
	omega_delay <= omega + omega_delay;
	sdata <= SINROM_TABLE(Conv_Integer(unsigned(omega_delay)));
	cdata <= COSROM_TABLE(Conv_Integer(unsigned(omega_delay)));
	
end if;
end process;

NCO_I <= cdata;
NCO_Q <= sdata;

end arch;

---

TestBench code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tb_NCO is
end tb_NCO;

architecture behavior of tb_NCO is

component NCO is
port(
	nrst, clk    : in std_logic;
	omega        : in std_logic_vector(7 downto 0);
	NCO_I, NCO_Q : out std_logic_vector(9 downto 0));
end component;

signal nrst, clk : std_logic;
signal omega : std_logic_vector(7 downto 0);
signal NCO_I, NCO_Q : std_logic_vector(9 downto 0);

begin

iNCO : NCO port map(
	nrst => nrst,
	clk => clk,
	omega => omega,
	NCO_I => NCO_I,
	NCO_Q => NCO_Q);

clkp : process
begin
	clk <= '1';
	wait for 20 ns;
	clk <= '0';
	wait for 20 ns;
end process;

nrstp : process
begin
	nrst <= '0';
	wait for 100 ns;
	nrst <= '1';
	wait;
end process;

iomega : process(nrst, clk)
begin
if nrst = '0' then
	omega <= (others => '0');
elsif clk = '1' and clk'event then
	omega <= "01000000";
end if;
end process;

end behavior;