목록전체 글 (295)

UOMOP

DownSampler using VHDL

RTL Code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity DnSample is generic ( DnRatio : integer := 4; Dwidth : integer := 10; LatchTime : integer := 7); port( nrst, upclk, dnclk : in std_logic; rdin, idin : in std_logic_vector((Dwidth-1) downto 0); rdout, idout : out std_logic_vector((Dwidth-1) downto 0)); end entity; architecture behavior of DnSample is signa..
Wireless Comm./VHDL 2022. 5. 12. 01:23
UpSampler using VHDL

RTL Code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity UpSample is generic( UpRatio : integer := 4; Dwidth : integer := 6); port( nrst, upclk : in std_logic; rdin, idin : in std_logic_vector((Dwidth-1) downto 0); rdout, idout : out std_logic_vector((Dwidth-1) downto 0)); end entity; architecture behavior of UpSample is signal cnt : integer range 0 to (UpRatio..
Wireless Comm./VHDL 2022. 5. 12. 01:22
16QAM (De)Mapper using VHDL

RTL Code(Mapper) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity QAM16mapper is port( nrst, sclk : in std_logic; inbits : in std_logic_vector(3 downto 0); rdata : out std_logic_vector(5 downto 0); idata : out std_logic_vector(5 downto 0)); end entity; architecture arch of QAM16mapper is constant pvalue1 : std_logic_vector(5 downto 0)..
Wireless Comm./VHDL 2022. 5. 12. 01:21
QPSK(4QAM) (De)Mapper using VHDL

RTL Code(Mapper) library ieee; use ieee.std_logic_1164.all; entity QAM4mapper is port( nrst, sclk : in std_logic; inbits : in std_logic_vector(1 downto 0); rdata : out std_logic_vector(5 downto 0); idata : out std_logic_vector(5 downto 0)); end entity; architecture arch of QAM4mapper is constant pvalue1 : std_logic_vector(5 downto 0) := "010000"; constant mvalue1 : std_logic_vector(5 downto 0) :..
Wireless Comm./VHDL 2022. 5. 12. 01:20
"Serial to Parallel" / "Parallel to Serial" using VHDL

RTL Code(S2P) library ieee; use ieee.std_logic_1164.all; entity s2p is generic (prate : in integer); port( nrst, sclk, pclk, inbit : in std_logic; outbits : out std_logic_vector((prate-1) downto 0)); end entity; architecture arch of s2p is signal inbuf : std_logic_vector((prate-1) downto 0); begin process(nrst, sclk) begin if nrst = '0' then inbuf '0'); elsif sclk'event and sclk = '1' then inbuf..
Wireless Comm./VHDL 2022. 5. 11. 22:42
Clock Generator using VHDL

RTL Code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clkgen is port( nrst, mclk : in std_logic; clk8x, clk4x, clk2x, clk1x : out std_logic); end entity; architecture arch of clkgen is signal cnt : std_logic_vector(3 downto 0); begin process(nrst, mclk) begin if nrst = '0' then cnt '0'); elsif mclk = '1' and mclk'event then cnt clk2x, clk1x => clk1x); clkp :..
Wireless Comm./VHDL 2022. 5. 11. 22:04
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