UOMOP

RTL Code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity rbgen is port( nrst, clk : in std_logic; outbit : out std_logic); end entity; architecture arch of rbgen is signal reg : std_logic_vector(11 downto 0); begin process(nrst, clk) begin if nrst = '0' then reg

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Testbench code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity tb_down_ver2 is end tb_down_ver2; architecture behavior of tb_down_ver2 is component clkgen port(nrst : in std_logic; mclk : in std_logic; clk8x : out std_logic; clk4x : out std_logic; clk2x : out std_logic; clk1x : out std_logic ); end component; component rbgen port(nrst : in std_logic; clk : in s..

RTL code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity downsample is port(nrst, clk4x, clk1x : in std_logic; rd4x, id4x : in std_logic_vector(5 downto 0); rd1x, id1x : out std_logic_vector(5 downto 0) ); end downsample; architecture arch of downsample is signal rd4xsym, id4xsym : std_logic_vector(5 downto 0); signal num_r1, num_r2, num_r3, num_r4 : std_logic_..

RTL code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity upsample is port(nrst, clk4x : in std_logic; rdata, idata : in std_logic_vector(5 downto 0); rd4x, id4x : out std_logic_vector(5 downto 0); selection : in std_logic_vector(1 downto 0) ); end upsample; architecture arch of upsample is signal r_upout, i_upout : std_logic_vector(5 downto 0); begin process(nr..

RTL code library ieee; use ieee.std_logic_1164.all; entity QPSKdemapper is port(nrst : in std_logic; pclk : in std_logic; rdata_de : in std_logic_vector(5 downto 0); idata_de : in std_logic_vector(5 downto 0); outdata_de : out std_logic_vector(1 downto 0) ); end entity; architecture arch of QPSKdemapper is signal finalbits : std_logic_vector(1 downto 0); begin process(nrst, pclk) begin if nrst =..