UOMOP
16QAM (De)Mapper using VHDL 본문
RTL Code(Mapper)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity QAM16mapper is
port(
nrst, sclk : in std_logic;
inbits : in std_logic_vector(3 downto 0);
rdata : out std_logic_vector(5 downto 0);
idata : out std_logic_vector(5 downto 0));
end entity;
architecture arch of QAM16mapper is
constant pvalue1 : std_logic_vector(5 downto 0) := "001000";
constant pvalue3 : std_logic_vector(5 downto 0) := "011000";
constant mvalue1 : std_logic_vector(5 downto 0) := "111000";
constant mvalue3 : std_logic_vector(5 downto 0) := "101000";
begin
process(nrst, sclk)
variable pr, pi : std_logic_vector(5 downto 0);
begin
if nrst = '0' then
rdata <= (others => '0');
idata <= (others => '0');
elsif sclk'event and sclk = '1' then
if(inbits(1) = '0') then
pr := pvalue3;
else
pr := pvalue1;
end if;
if(inbits(0) = '0') then
pi := pvalue3;
else
pi := pvalue1;
end if;
if(inbits(3) = '0') then
rdata <= pr;
else
rdata <= -pr;
end if;
if(inbits(2) = '0') then
idata <= pi;
else
idata <= -pi;
end if;
end if;
end process;
end arch;
RTL Code(DeMapper)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity QAM16demapper is
port(
nrst, sclk : in std_logic;
rdata, idata : std_logic_vector(5 downto 0);
outbits : out std_logic_vector(3 downto 0));
end entity;
architecture arch of QAM16demapper is
begin
process(nrst, sclk)
variable pr, pi : std_logic_vector(5 downto 0);
begin
if nrst = '0' then
outbits <= (others => '0');
elsif sclk'event and sclk = '1' then
if(rdata(5) = '0') then
outbits(3) <= '0';
pr := rdata;
else
outbits(3) <= '1';
pr := -rdata;
end if;
if(idata(5) = '0') then
outbits(2) <= '0';
pi := idata;
else
outbits(2) <= '1';
pi := -idata;
end if;
if(pr >= "010000") then
outbits(1) <= '0';
else
outbits(1) <= '1';
end if;
if(pi >= "010000") then
outbits(0) <= '0';
else
outbits(0) <= '1';
end if;
end if;
end process;
end arch;
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