DownSampler using VHDL

RTL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity DnSample is
generic ( DnRatio : integer := 4;
	  Dwidth  : integer := 10;
	  LatchTime : integer := 7);
port(
	nrst, upclk, dnclk : in std_logic;
	rdin, idin : in std_logic_vector((Dwidth-1) downto 0);

	rdout, idout : out std_logic_vector((Dwidth-1) downto 0));
end entity;

architecture behavior of DnSample is

signal cnt : integer range 0 to (DnRatio-1);
signal ir, ii : std_logic_vector((Dwidth-1) downto 0);

begin

process(nrst, upclk)
begin
if nrst = '0' then
	cnt <= 0;
	ir <= (others => '0');
	ii <= (others => '0');
elsif upclk = '1' and upclk'event then
	if(cnt = DnRatio-1) then
		cnt <= 0;
	else 
		cnt <= cnt + 1;
	end if;

	if(cnt = LatchTime) then
		ir <= rdin;
		ii <= idin;
	end if;
end if;
end process;

process(nrst, dnclk)
begin
if nrst = '0' then
	rdout <= (others => '0');
	idout <= (others => '0');
elsif dnclk = '1' and dnclk'event then
	rdout <= ir;
	idout <= ii;
end if;
end process;

end behavior;