Clock Generator using VHDL

RTL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clkgen is
port(
	nrst, mclk                 : in std_logic;
	clk8x, clk4x, clk2x, clk1x : out std_logic);
end entity;

architecture arch of clkgen is

signal cnt : std_logic_vector(3 downto 0);

begin
process(nrst, mclk)
begin
if nrst = '0' then
	cnt <= (others => '0');
elsif mclk = '1' and mclk'event then
	cnt <= cnt + 1;
end if;
end process;

clk8x <= cnt(0);
clk4x <= cnt(1);
clk2x <= cnt(2);
clk1x <= cnt(3);

end arch;

---

TestBench Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tb_clkgen is
end entity;

architecture behavior of tb_clkgen is
 
component clkgen is
port(
	nrst, mclk                 : in std_logic;
	clk8x, clk4x, clk2x, clk1x : out std_logic);
end component;

signal nrst, clk, clk8x, clk4x, clk2x, clk1x : std_logic;

begin
iclkgen : clkgen port map(
	nrst => nrst, 
	mclk => clk,
	clk8x => clk8x,
	clk4x => clk4x,
	clk2x => clk2x,
	clk1x => clk1x);

clkp : process
begin
	clk <= '1';
	wait for 20 ns;
	clk <= '0';
	wait for 20 ns;
end process;

nrstp : process
begin
	nrst <= '0';
	wait for 100 ns;
	nrst <= '1';
	wait;
end process;

end behavior;

---

Wave Capture