UOMOP

Ctrl + H

RTL code library ieee; use ieee.std_logic_1164.all; entity DQPSKmapper is port( nrst, clk : in std_logic; cdata : in std_logic_vector(1 downto 0); rout, iout: out std_logic_vector(5 downto 0)); end entity; architecture arch of DQPSKmapper is component QAM4mapper is port( nrst, sclk : in std_logic; inbits : in std_logic_vector(1 downto 0); rdata : out std_logic_vector(5 downto 0); idata : out std..

TestBench code library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mypackage.all; entity whole_12week is end entity; architecture behavior of whole_12week is component rbgen is port( nrst, clk : in std_logic; rbit : out std_logic); end component; component clkgen is port( nrst, mclk : in std_logic; clk8x, clk4x, clk2x, clk1x : out std_logic); end component..

TestBench library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mypackage.all; entity compare_PhaseSplit is end entity; architecture behavior of compare_PhaseSplit is component rbgen is port( nrst, clk : in std_logic; rbit : out std_logic); end component; component clkgen is port( nrst, mclk : in std_logic; clk8x, clk4x, clk2x, clk1x : out std_logic); end co..

RLT code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; library work; use work.mypackage.all; entity PhaseSplitter is port( nrst, clk : in std_logic; PS_Iin : in std_logic_vector(9 downto 0); PS_Iout, PS_Qout : out std_logic_vector(9 downto 0)); end entity; architecture arch of PhaseSplitter is signal reg : std_10b_array(14 downto 0); sign..

RTL(CPX_mul) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use work.mypackage.all; entity CPX_mul is port( nrst, clk : in std_logic; base_r, base_i : in std_logic_vector( 9 downto 0 ); NCO_r, NCO_i : in std_logic_vector( 9 downto 0 ); pass_r, pass_i : out std_logic_vector(9 downto 0)); end entity; architecture arch of CPX_mul is signal ba..