QPSK DeMapper using VHDL

RTL code

library ieee;
use ieee.std_logic_1164.all;

entity QPSKdemapper is
port(	nrst : in std_logic;
	pclk : in std_logic;
	rdata_de : in std_logic_vector(5 downto 0);
	idata_de : in std_logic_vector(5 downto 0);
	outdata_de : out std_logic_vector(1 downto 0)
	);
end entity;

architecture arch of QPSKdemapper is
signal finalbits : std_logic_vector(1 downto 0);

begin

process(nrst, pclk)
begin
	if nrst = '0' then
		finalbits <= (others => '0');
	elsif pclk = '1' and pclk'event then
		if rdata_de(5) = '0' then
			if idata_de(5) = '0' then
				finalbits <= "00";
			else
				finalbits <= "01";
			end if;
		else
			if idata_de(5) = '0' then
				finalbits <= "10";
			else
				finalbits <= "11";
			end if;
		end if;
	end if;
end process;

outdata_de <= finalbits;

end arch;

---

Testbench code

library ieee;
use ieee.std_logic_1164.all;

entity tb_QPSKdemapper is
end tb_QPSKdemapper;

architecture behavior of tb_QPSKdemapper is

component clkgen
   port(nrst  : in std_logic;
        mclk  : in std_logic;
   
        clk8x : out std_logic;   
        clk4x : out std_logic;
        clk2x : out std_logic;
        clk1x : out std_logic
   );
end component;

component rbgen
   port(nrst : in std_logic;
        clk  : in std_logic;

        rbit : out std_logic
   );
end component;

component Serial2Parallel
   port(nrst  : in std_logic;
        sclk  : in std_logic;
        pclk  : in std_logic;
        inbit : in std_logic;

        outbits : out std_logic_vector(1 downto 0)
   );
end component;

component QPSKmapper
	port(nrst : in std_logic;
	     pclk : in std_logic;
	     inbits : in std_logic_vector(1 downto 0);

	     rdata : out std_logic_vector(5 downto 0);
	     idata : out std_logic_vector(5 downto 0)
	);
end component;

component QPSKdemapper
	port(nrst, pclk : in std_logic;
	     rdata_de, idata_de : in std_logic_vector(5 downto 0);
	
	     outdata_de : out std_logic_vector(1 downto 0)
	);
end component;


signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;
signal rbit : std_logic;
signal outbits : std_logic_vector(1 downto 0);
signal rmapout, imapout : std_logic_vector(5 downto 0);

signal finalbits : std_logic_vector(1 downto 0);


begin 
iclkgen : clkgen port map(
      nrst  => nrst, 
      mclk  => mclk,
      clk8x => clk8x, 
      clk4x => clk4x,
      clk2x => clk2x,
      clk1x => clk1x
   );

irbgen : rbgen port map(
      nrst => nrst, 
      clk  => clk2x,
      rbit => rbit
   );

is2p : Serial2Parallel port map(
      nrst    => nrst, 
      sclk    => clk2x,
      pclk    => clk1x,
      inbit   => rbit,
      outbits => outbits
   );

iqmap : QPSKmapper port map(
	nrst => nrst,
	pclk => clk1x,
	inbits => outbits,

	rdata => rmapout,
	idata => imapout
	);

iqdemap : QPSKdemapper port map(
	nrst => nrst,
	pclk => clk1x,
	rdata_de => rmapout,
	idata_de => imapout,

	outdata_de => finalbits
	);

tb : process
begin
   mclk <= '1';
   wait for 20 ns;
   mclk <= '0';
   wait for 20 ns;
end process;

rstp : process
begin
   nrst <= '0';
   wait for 100 ns;
   nrst <= '1';
   wait;
end process;

end behavior;

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