Random Bit Generator using VHDL

RTL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rbgen is
port(
	nrst, clk : in std_logic;
	outbit    : out std_logic);
end entity;

architecture arch of rbgen is

signal reg : std_logic_vector(11 downto 0);

begin
process(nrst, clk)
begin
if nrst = '0' then
	reg <= "100000100101";
elsif clk = '1' and clk'event then
	reg(0) <= reg(5) xor reg(7) xor reg(10) xor reg(11);
	reg(11 downto 1) <= reg(10 downto 0);
end if;
end process;

outbit <= reg(11);

end arch;

---

TestBench Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tb_rbgen is
end tb_rbgen;

architecture behavior of tb_rbgen is

component rbgen is
port(
	nrst, clk : in std_logic;
	outbit    : out std_logic);
end component;

signal nrst, clk, rbit : std_logic;

begin
irbgen : rbgen port map(
	nrst => nrst,
	clk => clk,
	outbit => rbit);

clkp : process
begin
	clk <= '1';
	wait for 20 ns;
	clk <= '0';
	wait for 20 ns;
end process;

nrstp : process
begin
	nrst <= '0';
	wait for 100 ns;
	nrst <= '1';
	wait;
end process;

end behavior;

---

Wave Capture