"Serial to Parallel" / "Parallel to Serial" using VHDL

RTL Code(S2P)

library ieee;
use ieee.std_logic_1164.all;

entity s2p is
generic (prate : in integer);
port(
	nrst, sclk, pclk, inbit : in std_logic;
	outbits : out std_logic_vector((prate-1) downto 0));
end entity;

architecture arch of s2p is

signal inbuf : std_logic_vector((prate-1) downto 0);

begin

process(nrst, sclk)
begin
if nrst = '0' then
	inbuf <= (others => '0');
elsif sclk'event and sclk = '1' then
	inbuf((prate-1) downto 1) <= inbuf((prate-2) downto 0);
	inbuf(0) <= inbit;
end if;
end process;

process(nrst, pclk)
begin
if nrst = '0' then
	outbits <= (others => '0');
elsif pclk'event and pclk = '1' then
	outbits <= inbuf;
end if;
end process;

end arch;

---

RTL Code(P2S)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;

entity p2s is
generic(prate : in integer);
port(
	nrst, sclk : in std_logic;
	inbits : in std_logic_vector((prate-1) downto 0);

	outbit : out std_logic);
end entity;

architecture arch of p2s is

signal state : integer range 0 to (prate-1);

begin

process(nrst, sclk)
begin
if nrst = '0' then
	state <= (prate/2);
elsif sclk'event and sclk = '1' then
	if(state = prate-1) then
		state <= 0;
	else
		state <= state + 1;
	end if;
end if;
end process;

process(nrst, sclk)
begin
if nrst = '0' then
	outbit <= '0';
elsif sclk'event and sclk = '1' then
	outbit <= inbits((prate-1)-state);
end if;
end process;

end arch;

---

TestBench Code

library ieee;
use ieee.std_logic_1164.all;

entity tb_s2p2s is
end tb_s2p2s;

architecture behavior of tb_s2p2s is

-------------------------------------------------------------
component rbgen is
port(
	nrst, clk : in std_logic;
	outbit    : out std_logic);
end component;

component clkgen is
port(
	nrst, mclk                 : in std_logic;
	clk8x, clk4x, clk2x, clk1x : out std_logic);
end component;

component s2p is
generic (prate : in integer);
port(
	nrst, sclk, pclk, inbit : in std_logic;

	outbits : out std_logic_vector((prate-1) downto 0));
end component;

component p2s is
generic(prate : in integer);
port(
	nrst, sclk : in std_logic;
	inbits : in std_logic_vector((prate-1) downto 0);

	outbit : out std_logic);
end component;

-------------------------------------------------------------

signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;

signal rbit : std_logic;

signal outbits4 : std_logic_vector(3 downto 0);
signal finalbit4 : std_logic;

signal outbits2 : std_logic_vector(1 downto 0);
signal finalbit2 : std_logic;

-------------------------------------------------------------

begin
irbgen : rbgen port map(
	nrst => nrst,
	clk => clk4x,
	outbit => rbit);

iclkgen : clkgen port map(
	nrst => nrst,
	mclk => mclk,
	clk8x => clk8x,
	clk4x => clk4x,
	clk2x => clk2x,
	clk1x => clk1x);

is2p_4 : s2p
generic map(prate => 4)
port map(
	nrst => nrst,
	sclk => clk4x,
	pclk => clk1x,
	inbit => rbit,

	outbits => outbits4);

ip2s_4 : p2s
generic map(prate => 4)
port map(
	nrst => nrst,
	sclk => clk4x,
	inbits => outbits4,
	
	outbit => finalbit4);

is2p_2 : s2p
generic map(prate => 2)
port map(
	nrst => nrst,
	sclk => clk4x,
	pclk => clk2x,
	inbit => rbit,

	outbits => outbits2);

ip2s_2 : p2s
generic map(prate => 2)
port map(
	nrst => nrst,
	sclk => clk4x,
	inbits => outbits2,
	
	outbit => finalbit2);


mclkp : process
begin
	mclk <= '1';
	wait for 20 ns;
	mclk <= '0';
	wait for 20 ns;
end process;

nrstp : process
begin
	nrst <= '0';
	wait for 100 ns;
	nrst <= '1';
	wait;
end process;

end behavior;

---

Wave Capture