UpSampler using VHDL

RTL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity UpSample is
generic( UpRatio : integer := 4;
	 Dwidth  : integer := 6);

port(
	nrst, upclk : in std_logic;
	rdin, idin : in std_logic_vector((Dwidth-1) downto 0);

	rdout, idout : out std_logic_vector((Dwidth-1) downto 0));
end entity;

architecture behavior of UpSample is

signal cnt : integer range 0 to (UpRatio - 1);

begin

process(nrst, upclk)
begin
if nrst = '0' then
	cnt <= 0;
	rdout <= (others => '0');
	idout <= (others => '0');
elsif upclk = '1' and upclk'event then
	if(cnt = UpRatio-1) then
		cnt <= 0;
	else
		cnt <= cnt + 1;
	end if;

	if(cnt = 0) then
		rdout <= rdin;
		idout <= idin;
	else
		rdout <= (others => '0');
		idout <= (others => '0');
	end if;
end if;
end process;

end behavior;