QPSK(4QAM) (De)Mapper using VHDL

RTL Code(Mapper)

library ieee;
use ieee.std_logic_1164.all;

entity QAM4mapper is
port(
	nrst, sclk : in std_logic;
	inbits : in std_logic_vector(1 downto 0);

	rdata : out std_logic_vector(5 downto 0);
	idata : out std_logic_vector(5 downto 0));
end entity;

architecture arch of QAM4mapper is

constant pvalue1 : std_logic_vector(5 downto 0) := "010000";
constant mvalue1 : std_logic_vector(5 downto 0) := "110000";

begin

process(nrst, sclk)
begin
if nrst = '0' then
	rdata <= (others => '0');
	idata <= (others => '0');
elsif sclk'event and sclk = '1' then
	if(inbits(1) = '0') then
		rdata <= pvalue1;
	else
		rdata <= mvalue1;
	end if;

	if(inbits(0) = '0') then
		idata <= pvalue1;
	else
		idata <= mvalue1;
	end if;
end if;
end process;

end arch;

---

RTL Code(DeMapper)

library ieee;
use ieee.std_logic_1164.all;

entity QAM4demapper is
port(
	nrst, sclk : in std_logic;
	rdata, idata : in std_logic_vector(5 downto 0);

	outbits : out std_logic_vector(1 downto 0));
end entity;

architecture arch of QAM4demapper is

constant pvalue1 : std_logic_vector(5 downto 0) := "010000";
constant mvalue1 : std_logic_vector(5 downto 0) := "110000";

begin

process(nrst, sclk)
begin
if nrst = '0' then
	outbits <= (others => '0');
elsif sclk'event and sclk = '1' then
	if(rdata(5) = '0') then
		outbits(1) <= '0';
	else
		outbits(1) <= '1';
	end if;

	if(idata(5) = '0') then
		outbits(0) <= '0';
	else
		outbits(0) <= '1';
	end if;
end if;
end process;

end arch;