UpSampling using VHDL

RTL code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity upsample is
	port(	nrst, clk4x : in std_logic;
		rdata, idata : in std_logic_vector(5 downto 0);
		rd4x, id4x : out std_logic_vector(5 downto 0);
		selection : in std_logic_vector(1 downto 0)
	);
end upsample;



architecture arch of upsample is

signal r_upout, i_upout : std_logic_vector(5 downto 0);

begin

process(nrst, clk4x)
begin
	if nrst = '0' then
		r_upout <= (others => '0');
		i_upout <= (others => '0');
	elsif clk4x'event and clk4x = '1' then
		if selection = "10" then
			r_upout <= rdata;
			i_upout <= idata;
		else
			r_upout <= (others => '0');
			i_upout <= (others => '0');
		end if;
	end if;
end process;

rd4x <= r_upout;
id4x <= i_upout;

end arch;

---

Testbench code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tb_upsample is
end tb_upsample;

architecture behavior of tb_upsample is

component clkgen
   port(nrst  : in std_logic;
        mclk  : in std_logic;
   
        clk8x : out std_logic;   
        clk4x : out std_logic;
        clk2x : out std_logic;
        clk1x : out std_logic
   );
end component;

component rbgen
   port(nrst : in std_logic;
        clk  : in std_logic;

        rbit : out std_logic
   );
end component;

component Serial2Parallel
   port(nrst  : in std_logic;
        sclk  : in std_logic;
        pclk  : in std_logic;
        inbit : in std_logic;

        outbits : out std_logic_vector(1 downto 0)
   );
end component;

component QPSKmapper
	port(nrst : in std_logic;
	     pclk : in std_logic;
	     inbits : in std_logic_vector(1 downto 0);

	     rdata : out std_logic_vector(5 downto 0);
	     idata : out std_logic_vector(5 downto 0)
	);
end component;

component upsample
	port(	nrst, clk4x : in std_logic;
		rdata, idata : in std_logic_vector(5 downto 0);
		rd4x, id4x : out std_logic_vector(5 downto 0);
		selection : in std_logic_vector(1 downto 0)
	);
end component;

component twobitcounter
	port(	nrst, clk4x : in std_logic;
		cntout_2 : out std_logic_vector(1 downto 0)
	);
end component;


signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;
signal rbit : std_logic;

signal outbits : std_logic_vector(1 downto 0);

signal rmapout, imapout : std_logic_vector(5 downto 0);

signal r_upout, i_upout : std_logic_vector(5 downto 0);

signal cnt_2 : std_logic_vector(1 downto 0);




begin 
iclkgen : clkgen port map(
      nrst  => nrst, 
      mclk  => mclk,
      clk8x => clk8x, 
      clk4x => clk4x,
      clk2x => clk2x,
      clk1x => clk1x
   );

irbgen : rbgen port map(
      nrst => nrst, 
      clk  => clk2x,
      rbit => rbit
   );

is2p : Serial2Parallel port map(
      nrst    => nrst, 
      sclk    => clk2x,
      pclk    => clk1x,
      inbit   => rbit,
      outbits => outbits
   );

iqmap : QPSKmapper port map(
	nrst => nrst,
	pclk => clk1x,
	inbits => outbits,

	rdata => rmapout,
	idata => imapout
	);

icnt2 : twobitcounter port map(
	nrst => nrst,
	clk4x => clk4x,
	cntout_2 => cnt_2
	);


iupsam : upsample port map(
	nrst => nrst,
	clk4x => clk4x,
	rdata => rmapout,
	idata => imapout,
	rd4x => r_upout,
	id4x => i_upout,
	selection => cnt_2
	);


tb : process
begin
   mclk <= '1';
   wait for 20 ns;
   mclk <= '0';
   wait for 20 ns;
end process;

rstp : process
begin
   nrst <= '0';
   wait for 100 ns;
   nrst <= '1';
   wait;
end process;

end behavior;

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