The Whole Process using VHDL

Testbench code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tb_down_ver2 is
end tb_down_ver2;

architecture behavior of tb_down_ver2 is

component clkgen
   port(nrst  : in std_logic;
        mclk  : in std_logic;
   
        clk8x : out std_logic;   
        clk4x : out std_logic;
        clk2x : out std_logic;
        clk1x : out std_logic
   );
end component;

component rbgen
   port(nrst : in std_logic;
        clk  : in std_logic;

        rbit : out std_logic
   );
end component;

component Serial2Parallel
   port(nrst  : in std_logic;
        sclk  : in std_logic;
        pclk  : in std_logic;
        inbit : in std_logic;

        outbits : out std_logic_vector(1 downto 0)
   );
end component;

component QPSKmapper
	port(nrst : in std_logic;
	     pclk : in std_logic;
	     inbits : in std_logic_vector(1 downto 0);

	     rdata : out std_logic_vector(5 downto 0);
	     idata : out std_logic_vector(5 downto 0)
	);
end component;

component upsample
	port(	nrst, clk4x : in std_logic;
		rdata, idata : in std_logic_vector(5 downto 0);
		rd4x, id4x : out std_logic_vector(5 downto 0);
		selection : in std_logic_vector(1 downto 0)
	);
end component;

component onebitcounter
	port(	nrst : in std_logic;
		sclk : in std_logic;

		cntout : out std_logic_vector(0 downto 0)
	);
end component;

component twobitcounter
	port(	nrst, clk4x : in std_logic;
		cntout_2 : out std_logic_vector(1 downto 0)
	);
end component;

component new_downsample
	port(	nrst, clk4x, clk1x : in std_logic;
		rd4x, id4x : in std_logic_vector(5 downto 0);
		r_dnout, i_dnout : out std_logic_vector(5 downto 0)
	);
end component;

component QPSKdemapper
	port(	nrst : in std_logic;
		pclk : in std_logic;
		rdata_de : in std_logic_vector(5 downto 0);
		idata_de : in std_logic_vector(5 downto 0);
		outdata_de : out std_logic_vector(1 downto 0)
	);
end component;

component Parallel2Series
	port(	nrst   : in std_logic;
		sclk   : in std_logic;
		inbits : in std_logic_vector(1 downto 0);
		sel    : in std_logic_vector(0 downto 0);
	
		finalbit : out std_logic
	);
end component;




signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;
signal rbit : std_logic;

signal state : std_logic_vector(0 downto 0);

signal outbits : std_logic_vector(1 downto 0);

signal rmapout, imapout : std_logic_vector(5 downto 0);

signal r_upout, i_upout : std_logic_vector(5 downto 0);

signal cnt_2 : std_logic_vector(1 downto 0);

signal finalbits : std_logic_vector(1 downto 0);
signal finalbit : std_logic;

signal cnt : integer range 0 to 3;
signal sel : std_logic;
signal r_dndata, i_dndata : std_logic_vector(5 downto 0);


begin 
iclkgen : clkgen port map(
      nrst  => nrst, 
      mclk  => mclk,
      clk8x => clk8x, 
      clk4x => clk4x,
      clk2x => clk2x,
      clk1x => clk1x
   );

irbgen : rbgen port map(
      nrst => nrst, 
      clk  => clk2x,
      rbit => rbit
   );

is2p : Serial2Parallel port map(
      nrst    => nrst, 
      sclk    => clk2x,
      pclk    => clk1x,
      inbit   => rbit,
      outbits => outbits
   );

icnt : onebitcounter port map(
	nrst => nrst,
	sclk => clk2x,
	cntout => state
	);

iqmap : QPSKmapper port map(
	nrst => nrst,
	pclk => clk1x,
	inbits => outbits,

	rdata => rmapout,
	idata => imapout
	);

icnt2 : twobitcounter port map(
	nrst => nrst,
	clk4x => clk4x,
	cntout_2 => cnt_2
	);


iupsam : upsample port map(
	nrst => nrst,
	clk4x => clk4x,
	rdata => rmapout,
	idata => imapout,
	rd4x => r_upout,
	id4x => i_upout,
	selection => cnt_2
	);

idwsam : new_downsample port map(
	nrst => nrst,
	clk4x => clk4x,
	clk1x => clk1x,
	rd4x => r_upout,
	id4x => i_upout,
	r_dnout => r_dndata,
	i_dnout => i_dndata
	);

iqdemap : QPSKdemapper port map(
	nrst => nrst,
	pclk => clk1x,
	rdata_de => r_dndata,
	idata_de => i_dndata,
	outdata_de => finalbits
	);

ip2s : Parallel2Series port map(
	nrst => nrst,
	sclk => clk2x,
	inbits => finalbits,
	sel => state,
	finalbit => finalbit
);


tb : process
begin
   mclk <= '1';
   wait for 20 ns;
   mclk <= '0';
   wait for 20 ns;
end process;

rstp : process
begin
   nrst <= '0';
   wait for 100 ns;
   nrst <= '1';
   wait;
end process;



end behavior;

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