DownSampling using VHDL

RTL code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity downsample is
port(	nrst, clk4x, clk1x : in std_logic;
	rd4x, id4x : in std_logic_vector(5 downto 0);

	rd1x, id1x : out std_logic_vector(5 downto 0)
	);
end downsample;

architecture arch of downsample is

signal rd4xsym, id4xsym : std_logic_vector(5 downto 0);
signal num_r1, num_r2, num_r3, num_r4 : std_logic_vector(5 downto 0);
signal num_i1, num_i2, num_i3, num_i4 : std_logic_vector(5 downto 0);
signal dsel : std_logic_vector(1 downto 0);
signal cnt_2 : std_logic_vector(1 downto 0);
signal buf_r, buf_i : std_logic_vector(5 downto 0);

begin
	
process(nrst, clk4x)
begin
	if nrst = '0' then
		num_r1 <= (others => '0'); num_i1 <= (others => '0');
		num_r2 <= (others => '0'); num_i2 <= (others => '0');
		num_r3 <= (others => '0'); num_i3 <= (others => '0');
		num_r4 <= (others => '0'); num_i4 <= (others => '0');

	elsif clk4x = '1' and clk4x'event then

		if cnt_2 = "11" then
			num_r1 <= rd4x; num_i1 <= id4x;
			num_r2 <= (others => '0'); num_i2 <= (others => '0');
			num_r3 <= (others => '0'); num_i3 <= (others => '0');
			num_r4 <= (others => '0'); num_i4 <= (others => '0');
			dsel <= "00";
	
		elsif cnt_2 = "00" then
			num_r2 <= rd4x; num_i2 <= id4x;
			num_r1 <= (others => '0'); num_i1 <= (others => '0');
			num_r3 <= (others => '0'); num_i3 <= (others => '0');
			num_r4 <= (others => '0'); num_i4 <= (others => '0');
			dsel <= "01";

		elsif cnt_2 = "01" then
			num_r3 <= rd4x; num_i3 <= id4x;
			num_r1 <= (others => '0'); num_i1 <= (others => '0');
			num_r2 <= (others => '0'); num_i2 <= (others => '0');
			num_r4 <= (others => '0'); num_i4 <= (others => '0');
			dsel <= "10";

		elsif cnt_2 = "10" then
			num_r4 <= rd4x; num_i4 <= id4x;
			num_r1 <= (others => '0'); num_i1 <= (others => '0');
			num_r2 <= (others => '0'); num_i2 <= (others => '0');
			num_r3 <= (others => '0'); num_i3 <= (others => '0');
			dsel <= "11";
		end if;
	end if;	

end process;

process(nrst, clk4x)
begin
	if nrst = '0' then
		cnt_2 <= (others => '0');
	elsif clk4x = '1' and clk4x'event then
		cnt_2 <= cnt_2 + 1;
	end if;
end process;

process(nrst, clk1x)
begin

	if nrst = '0' then
		buf_r <= (others => '0');
		buf_i <= (others => '0');
	elsif (clk1x = '1' or clk1x'event) and dsel = "00" then
			buf_r <= num_r1;
			buf_i <= num_i1;
	end if;
end process;

process(nrst, clk1x)
begin
	if nrst = '0' then
		rd4xsym <= (others => '0');
		id4xsym <= (others => '0');
	elsif clk1x = '1' and clk1x'event then
		rd4xsym <= buf_r;
		id4xsym <= buf_i;
	end if;
end process;

rd1x <= rd4xsym;
id1x <= id4xsym;

end arch;

---

Testbench code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tb_downsample is
end tb_downsample;

architecture behavior of tb_downsample is

component clkgen
   port(nrst  : in std_logic;
        mclk  : in std_logic;
   
        clk8x : out std_logic;   
        clk4x : out std_logic;
        clk2x : out std_logic;
        clk1x : out std_logic
   );
end component;

component rbgen
   port(nrst : in std_logic;
        clk  : in std_logic;

        rbit : out std_logic
   );
end component;

component Serial2Parallel
   port(nrst  : in std_logic;
        sclk  : in std_logic;
        pclk  : in std_logic;
        inbit : in std_logic;

        outbits : out std_logic_vector(1 downto 0)
   );
end component;

component QPSKmapper
	port(nrst : in std_logic;
	     pclk : in std_logic;
	     inbits : in std_logic_vector(1 downto 0);

	     rdata : out std_logic_vector(5 downto 0);
	     idata : out std_logic_vector(5 downto 0)
	);
end component;

component upsample
	port(	nrst, clk4x : in std_logic;
		rdata, idata : in std_logic_vector(5 downto 0);
		rd4x, id4x : out std_logic_vector(5 downto 0);
		selection : in std_logic_vector(1 downto 0)
	);
end component;

component onebitcounter
	port(	nrst : in std_logic;
		sclk : in std_logic;

		cntout : out std_logic_vector(0 downto 0)
	);
end component;

component twobitcounter
	port(	nrst, clk4x : in std_logic;
		cntout_2 : out std_logic_vector(1 downto 0)
	);
end component;

component downsample
	port(	nrst, clk4x, clk1x : in std_logic;
		rd4x, id4x : in std_logic_vector(5 downto 0);
		--dsel : in std_logic_vector(1 downto 0);

		rd1x, id1x : out std_logic_vector(5 downto 0)
	);
end component;

component QPSKdemapper
	port(	nrst : in std_logic;
		pclk : in std_logic;
		rdata_de : in std_logic_vector(5 downto 0);
		idata_de : in std_logic_vector(5 downto 0);
		outdata_de : out std_logic_vector(1 downto 0)
	);
end component;

component Parallel2Series
	port(	nrst   : in std_logic;
		sclk   : in std_logic;
		inbits : in std_logic_vector(1 downto 0);
		sel    : in std_logic_vector(0 downto 0);
	
		finalbit : out std_logic
	);
end component;




signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;
signal rbit : std_logic;

signal state : std_logic_vector(0 downto 0);

signal outbits : std_logic_vector(1 downto 0);

signal rmapout, imapout : std_logic_vector(5 downto 0);

signal r_upout, i_upout : std_logic_vector(5 downto 0);

signal cnt_2 : std_logic_vector(1 downto 0);

signal rd4xsym, id4xsym : std_logic_vector(5 downto 0);

signal finalbits : std_logic_vector(1 downto 0);
signal finalbit : std_logic;




begin 
iclkgen : clkgen port map(
      nrst  => nrst, 
      mclk  => mclk,
      clk8x => clk8x, 
      clk4x => clk4x,
      clk2x => clk2x,
      clk1x => clk1x
   );

irbgen : rbgen port map(
      nrst => nrst, 
      clk  => clk2x,
      rbit => rbit
   );

is2p : Serial2Parallel port map(
      nrst    => nrst, 
      sclk    => clk2x,
      pclk    => clk1x,
      inbit   => rbit,
      outbits => outbits
   );

icnt : onebitcounter port map(
	nrst => nrst,
	sclk => clk2x,
	cntout => state
	);

iqmap : QPSKmapper port map(
	nrst => nrst,
	pclk => clk1x,
	inbits => outbits,

	rdata => rmapout,
	idata => imapout
	);

icnt2 : twobitcounter port map(
	nrst => nrst,
	clk4x => clk4x,
	cntout_2 => cnt_2
	);


iupsam : upsample port map(
	nrst => nrst,
	clk4x => clk4x,
	rdata => rmapout,
	idata => imapout,
	rd4x => r_upout,
	id4x => i_upout,
	selection => cnt_2
	);

idwsam : downsample port map(
	nrst => nrst,
	clk4x => clk4x,
	clk1x => clk1x,
	rd4x => r_upout,
	id4x => i_upout,
	rd1x => rd4xsym,
	id1x => id4xsym
	);

iqdemap : QPSKdemapper port map(
	nrst => nrst,
	pclk => clk1x,
	rdata_de => rd4xsym,
	idata_de => id4xsym,
	outdata_de => finalbits
	);

ip2s : Parallel2Series port map(
	nrst => nrst,
	sclk => clk2x,
	inbits => finalbits,
	sel => state,
	finalbit => finalbit
);


tb : process
begin
   mclk <= '1';
   wait for 20 ns;
   mclk <= '0';
   wait for 20 ns;
end process;

rstp : process
begin
   nrst <= '0';
   wait for 100 ns;
   nrst <= '1';
   wait;
end process;



end behavior;

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