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TestBench Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_QAMUpDown is
end entity;

architecture behavior of tb_QAMUpDown is

------------------------------------------------------------------

component rbgen is
port(
	nrst, clk : in std_logic;
	rbit    : out std_logic);
end component;

component clkgen is
port(
	nrst, mclk                 : in std_logic;
	clk8x, clk4x, clk2x, clk1x : out std_logic);
end component;

component s2p is
generic (prate : in integer);
port(
	nrst, sclk, pclk, inbit : in std_logic;
	outbits : out std_logic_vector((prate-1) downto 0));
end component;

component QAM16mapper is
port(
	nrst, sclk : in std_logic;
	inbits : in std_logic_vector(3 downto 0);
	
	rdata : out std_logic_vector(5 downto 0);
	idata : out std_logic_vector(5 downto 0));
end component;

component QAM16demapper is
port(
	nrst, sclk : in std_logic;
	rdata, idata : std_logic_vector(5 downto 0);

	outbits : out std_logic_vector(3 downto 0));
end component;

component QAM4mapper is
port(
	nrst, sclk : in std_logic;
	inbits : in std_logic_vector(1 downto 0);

	rdata : out std_logic_vector(5 downto 0);
	idata : out std_logic_vector(5 downto 0));
end component;

component QAM4demapper is
port(
	nrst, sclk : in std_logic;
	rdata, idata : in std_logic_vector(5 downto 0);

	outbits : out std_logic_vector(1 downto 0));
end component;

component p2s is
generic(prate : in integer);
port(
	nrst, sclk : in std_logic;
	inbits : in std_logic_vector((prate-1) downto 0);

	outbit : out std_logic);
end component;

component UpSample is
generic( UpRatio : integer := 4;
	 Dwidth  : integer := 6);

port(
	nrst, upclk : in std_logic;
	rdin, idin : in std_logic_vector((Dwidth-1) downto 0);

	rdout, idout : out std_logic_vector((Dwidth-1) downto 0));
end component;

component DnSample is
generic ( DnRatio : integer := 4;
	  Dwidth  : integer := 10;
	  LatchTime : integer := 7);
port(
	nrst, upclk, dnclk : in std_logic;
	rdin, idin : in std_logic_vector((Dwidth-1) downto 0);

	rdout, idout : out std_logic_vector((Dwidth-1) downto 0));
end component;

------------------------------------------------------------------

signal nrst, mclk, clk8x, clk4x, clk2x, clk1x : std_logic;

signal rbit : std_logic;

signal QAM16_S2Pout : std_logic_vector(3 downto 0);
signal QAM16_rmapout, QAM16_imapout : std_logic_vector(5 downto 0);
signal QAM16_rupout, QAM16_iupout : std_logic_vector(5 downto 0);
signal QAM16_rdnout, QAM16_idnout : std_logic_vector(5 downto 0);

signal QAM16_dmapbits : std_logic_vector(3 downto 0);
signal QAM16_FinalBit : std_logic;

signal QPSK_S2Pout : std_logic_vector(1 downto 0);
signal QPSK_rmapout, QPSK_imapout : std_logic_vector(5 downto 0);
signal QPSK_rupout, QPSK_iupout : std_logic_vector(5 downto 0);
signal QPSK_rdnout, QPSK_idnout : std_logic_vector(5 downto 0);
signal QPSK_dmapbits : std_logic_vector(1 downto 0);
signal QPSK_FinalBit : std_logic;

begin
irbgen : rbgen port map(
	nrst => nrst,
	clk => clk4x,
	rbit => rbit);

iclkgen : clkgen port map(
	nrst => nrst,
	mclk => mclk,
	clk8x => clk8x,
	clk4x => clk4x,
	clk2x => clk2x,
	clk1x => clk1x);

is2p : s2p
generic map(prate => 4)
port map(
	nrst => nrst,
	sclk => clk4x,
	pclk => clk1x,
	inbit => rbit,

	outbits => QAM16_S2Pout);

iq16mod : QAM16mapper port map(
	nrst => nrst,
	sclk => clk1x,
	inbits => QAM16_S2Pout,

	rdata => QAM16_rmapout,
	idata => QAM16_imapout);

iup8 : UpSample
generic map(UpRatio => 8,
	    Dwidth  => 6)
port map(
	nrst => nrst,
	upclk => clk8x,
	rdin => QAM16_rmapout,
	idin => QAM16_imapout,

	rdout => QAM16_rupout,
	idout => QAM16_iupout);

idn8 : DnSample
generic map(DnRatio => 8, 
	    Dwidth => 6,
	    LatchTime => 1)
port map(
	nrst => nrst,
	upclk => clk8x,
	dnclk => clk1x,
	rdin => QAM16_rupout,
	idin => QAM16_iupout,

	rdout => QAM16_rdnout,
	idout => QAM16_idnout);

iq16demod : QAM16demapper
port map(
	nrst => nrst,
	sclk => clk1x,
	rdata => QAM16_rdnout,
	idata => QAM16_idnout,

	outbits => QAM16_dmapbits);

ip2s : p2s
generic map(prate => 4)
port map(
	nrst => nrst,
	sclk => clk4x,
	inbits => QAM16_dmapbits,

	outbit => QAM16_FinalBit);

is2p2 : s2p
generic map(prate => 2)
port map(
	nrst => nrst,
	sclk => clk4x,
	pclk => clk2x,
	inbit => rbit,

	outbits => QPSK_S2Pout);

iq4mod : QAM4mapper port map(
	nrst => nrst,
	sclk => clk2x,
	inbits => QPSK_S2Pout,

	rdata => QPSK_rmapout,
	idata => QPSK_imapout);

iup4 : UpSample
generic map(UpRatio => 4,
	    Dwidth  => 6)
port map(
	nrst => nrst,
	upclk => clk8x,
	rdin => QPSK_rmapout,
	idin => QPSK_imapout,

	rdout => QPSK_rupout,
	idout => QPSK_iupout);

idn4 : DnSample
generic map(DnRatio => 4,
	    Dwidth  => 6,
	    LatchTime => 1)
port map(
	nrst => nrst,
	upclk => clk8x,
	dnclk => clk2x,
	rdin => QPSK_rupout,
	idin => QPSK_iupout,

	rdout => QPSK_rdnout,
	idout => QPSK_idnout);

iq4demod : QAM4demapper port map(
	nrst => nrst,
	sclk => clk2x,
	rdata => QPSK_rdnout,
	idata => QPSK_idnout,

	outbits => QPSK_dmapbits);

ip2s2 : p2s
generic map(prate => 2)
port map(
	nrst => nrst,
	sclk => clk4x,
	inbits => QPSK_dmapbits,

	outbit => QPSK_FinalBit);

mclkp : process
begin
	mclk <= '1';
	wait for 20 ns;
	mclk <= '0';
	wait for 20 ns;
end process;

nrstp : process
begin
	nrst <= '0';
	wait for 100 ns;
	nrst <= '1';
	wait;
end process;

end behavior;

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