DQPSK DeMapper

RTL code

library ieee;
use ieee.std_logic_1164.all;

entity DQPSKdemapper is
port(
	nrst, clk : in std_logic;
	rdata, idata : in std_logic_vector(5 downto 0);

	outbits : out std_logic_vector(1 downto 0));
end entity;

architecture arch of DQPSKdemapper is

component QAM4demapper is
port(
	nrst, sclk : in std_logic;
	rdata, idata : in std_logic_vector(5 downto 0);

	outbits : out std_logic_vector(1 downto 0));
end component;

signal y, cdata, pdata : std_logic_vector(1 downto 0);

begin

iqpskdemap : QAM4demapper
port map(
	nrst => nrst,
	sclk => clk,
	rdata => rdata,
	idata => idata,
	outbits => cdata);



process(nrst, clk)
begin

if nrst = '0' then
	pdata <= "00";
elsif clk'event and clk = '1' then
	pdata <= cdata;
end if;
end process;



process(cdata, pdata)
begin

if pdata = "00" then
	y <= cdata;

elsif pdata = "01" then
	if cdata = "00" then
		y <= "10";
	elsif cdata = "01" then
		y <= "00";
	elsif cdata = "10" then
		y <= "11";
	else
		y <= "01";
	end if;

elsif pdata = "10" then
	if cdata = "00" then
		y <= "01";
	elsif cdata = "01" then
		y <= "11";
	elsif cdata = "10" then
		y <= "00";
	else
		y <= "10";
	end if;

else
	if cdata = "00" then
		y <= "11";
	elsif cdata = "01" then
		y <= "10";
	elsif cdata = "10" then
		y <= "01";
	else
		y <= "00";
	end if;
end if;
end process;

outbits <= y;

end arch;

---

TestBench code

library ieee;
use ieee.std_logic_1164.all;

entity tb_DQPSKdemapper is
end entity;

architecture behavior of tb_DQPSKdemapper is

component clkgen is
port(
	nrst, mclk                 : in std_logic;
	clk8x, clk4x, clk2x, clk1x : out std_logic);
end component;

component rbgen is
port(
	nrst, clk : in std_logic;
	rbit    : out std_logic);
end component;

component s2p is
generic (prate : in integer);
port(
	nrst, sclk, pclk, inbit : in std_logic;
	outbits : out std_logic_vector((prate-1) downto 0));
end component;

component DQPSKmapper is
port(
	nrst, clk : in std_logic;
	cdata     : in std_logic_vector(1 downto 0);
	rout, iout: out std_logic_vector(5 downto 0));
end component;

component DQPSKdemapper is
port(
	nrst, clk : in std_logic;
	rdata, idata : in std_logic_vector(5 downto 0);

	outbits : out std_logic_vector(1 downto 0));
end component;

component p2s is
generic(prate : in integer);
port(
	nrst, sclk : in std_logic;
	inbits : in std_logic_vector((prate-1) downto 0);

	outbit : out std_logic);
end component;

signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;
signal rbit : std_logic;
signal s2pout : std_logic_vector(1 downto 0);
signal rmapout, imapout : std_logic_vector(5 downto 0);
signal demapout : std_logic_vector(1 downto 0);
signal p2sout : std_logic;

begin

iclkgen : clkgen 
port map(
   nrst => nrst,
   mclk => mclk,
   clk8x => clk8x,
   clk4x => clk4x,
   clk2x => clk2x,
   clk1x => clk1x);

irbgen : rbgen
port map(
   nrst => nrst,
   clk => clk4x,

   rbit => rbit);

is2p : s2p
generic map(prate => 2)
port map(
   nrst => nrst,
   sclk => clk4x,
   pclk => clk2x,
   inbit => rbit,
	
   outbits => s2pout);

idqpskmap : DQPSKmapper
port map(
    
   nrst => nrst,
   clk => clk2x,
   cdata => s2pout,
   rout => rmapout,
   iout => imapout);

idqpskdemap : DQPSKdemapper
port map(
	nrst => nrst,
	clk => clk2x,
	rdata => rmapout,
	idata => imapout,

	outbits => demapout);

ip2s : p2s
generic map(prate => 2)
port map(
	nrst => nrst,
	sclk => clk4x,
	inbits => demapout,

	outbit => p2sout);


mclkp : process
begin
   mclk <= '1';
   wait for 20 ns;
   mclk <= '0';
   wait for 20 ns;
end process;


nrstp : process
begin
   nrst <= '0';
   wait for 100 ns;
   nrst <= '1';
   wait;
end process;

end behavior;

---

Wave Capture