Final

RTL(QPSK_PED)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

library work;
use work.mypackage.all;

entity QPSK_PED is
port(
	nrst : in std_logic;
	clk : in std_logic;
	rin, iin : in std_logic_vector(9 downto 0);
	Perr : out std_logic_vector(9 downto 0));
end entity;

architecture arch of QPSK_PED is

signal Rsign, Isign : std_logic;

begin
	Rsign <= rin(9);
	Isign <= iin(9);

process(nrst, clk)
begin

if nrst = '0' then
	Perr <= (others => '0');
elsif clk = '1' and clk'event then
	if(Rsign = '0') then
		if(Isign = '0') then
			Perr <= iin - rin;
		else
			Perr <= iin + rin;
		end if;
	else
		if(Isign = '0') then
			Perr <= -iin - rin;
		else
			Perr <= rin - iin;
		end if;
	end if;
end if;
end process;

end arch;

---

RTL(QPSK_LoopFilter)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity QPSK_LoopFilter is
port(
	nrst : in std_logic;
	clk : in std_logic;
	Perr : in std_logic_vector(9 downto 0);
	LFout : out std_logic_vector(25 downto 0));
end entity;

architecture arch of QPSK_LoopFilter is

signal K1Perr : std_logic_vector(17 downto 0);
signal Acc : std_logic_vector(25 downto 0);

begin

K1Perr <= sxt(Perr, 18);

process(nrst, clk)
begin

if nrst = '0' then
	Acc <= (others => '0');
elsif clk = '1' and clk'event then
	Acc <= Acc + Perr;
end if;
end process;

LFout <= K1Perr & "00000000" + Acc;

end arch;

---

RTL(QPSK_NCO)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity QPSK_NCO is
port(
	nrst, clk : in std_logic;
	omega : in std_logic_vector(25 downto 0);
	LFout : in std_logic_vector(25 downto 0);

 	NCO_I, NCO_Q : out std_logic_vector(9 downto 0));
end entity;

architecture arch of QPSK_NCO is

component NCOtable is
port(
	nrst, clk    : in std_logic;
	address      : in std_logic_vector(7 downto 0);
	NCO_I, NCO_Q : out std_logic_vector(9 downto 0));
end component;

signal NCO_Acc, dphase : std_logic_vector(25 downto 0);
signal addr : std_logic_vector(7 downto 0);

begin

process(nrst, clk)
begin 
if nrst = '0' then
	dphase <= (others => '0');
elsif clk = '1' and clk'event then
	dphase <= LFout + omega;
end if;
end process;

process(nrst, clk)
begin

if nrst = '0' then
	NCO_Acc <= (others => '0');
elsif clk = '1' and clk'event then
	NCO_Acc <= NCO_Acc + dphase;
end if;
end process;

addr <= NCO_Acc(25 downto 18);

iNCOtable : NCOtable
port map(
nrst => nrst,
clk => clk,
address => addr,
NCO_I => NCO_I,
NCO_Q => NCO_Q);
end arch;

---

RTL(Down Conversion NCO CR)

library ieee;
use ieee.std_logic_1164.all;

entity DnConv_NCO_CR is
port(
	nrst, clk1x, clk4x : in std_logic;
	pass_r, pass_i : in std_logic_vector(9 downto 0);
	base_r1x, base_i1x : in std_logic_vector(9 downto 0);

	base_r, base_i : out std_logic_vector(9 downto 0));
end entity;

architecture arch of DnConv_NCO_CR is

component CPX_mul is
port(
	nrst, clk      : in std_logic;
	base_r, base_i : in std_logic_vector( 9 downto 0 );
	NCO_r, NCO_i   : in std_logic_vector( 9 downto 0 );

	pass_r, pass_i : out std_logic_vector(9 downto 0));
end component;

component QPSK_PED is
port(
	nrst : in std_logic;
	clk : in std_logic;
	rin, iin : in std_logic_vector(9 downto 0);
	Perr : out std_logic_vector(9 downto 0));
end component;

component QPSK_LoopFilter is
port(
	nrst : in std_logic;
	clk : in std_logic;
	Perr : in std_logic_vector(9 downto 0);
	LFout : out std_logic_vector(25 downto 0));
end component;

component CPX_comp_mul is
port(
	nrst, clk      : in std_logic;
	pass_r, pass_i : in std_logic_vector( 9 downto 0 );
	NCO_r, NCO_i   : in std_logic_vector( 9 downto 0 );

	base_r, base_i : out std_logic_vector(9 downto 0));
end component;

component QPSK_NCO is
port(
	nrst, clk : in std_logic;
	omega : in std_logic_vector(25 downto 0);
	LFout : in std_logic_vector(25 downto 0);

 	NCO_I, NCO_Q : out std_logic_vector(9 downto 0));
end component;


signal Perr : std_logic_vector(9 downto 0);
signal LFout, omega : std_logic_vector(25 downto 0);
signal NCO_I, NCO_Q : std_logic_vector(9 downto 0);

begin

iperr : QPSK_PED
port map(
	nrst => nrst,
	clk => clk1x,
	rin => base_r1x,
	iin => base_i1x,

	Perr => Perr);

ilf : QPSK_LoopFilter
port map(
	nrst => nrst,
	clk => clk1x,
	Perr => Perr,
	LFout => LFout);

omega <= "01000000100000000000000000";

inco : QPSK_NCO
port map(
	nrst => nrst,
	clk => clk4x,

	omega => omega,
	LFout => LFout,

	NCO_I => NCO_I,
	NCO_Q => NCO_Q);



icpxmul : CPX_comp_mul
port map(
	nrst => nrst,
	clk => clk4x,
	pass_r => pass_r,
	pass_i => pass_i,

	NCO_r => NCO_I,
	NCO_i => NCO_Q,
	base_r => base_r,
	base_i => base_i
);
end arch;

---

TestBench code(Final Project)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.mypackage.all;

entity final_project is
end entity;

architecture behavior of final_project is

component rbgen is
port(
	nrst, clk : in std_logic;
	rbit    : out std_logic);
end component;


component clkgen is
port(
	nrst, mclk                 : in std_logic;
	clk8x, clk4x, clk2x, clk1x : out std_logic);
end component;


component s2p is
generic (prate : in integer);
port(
	nrst, sclk, pclk, inbit : in std_logic;
	outbits : out std_logic_vector((prate-1) downto 0));
end component;


component DQPSKmapper is
port(
	nrst, clk : in std_logic;
	cdata     : in std_logic_vector(1 downto 0);
	rout, iout: out std_logic_vector(5 downto 0));
end component;


component DQPSKdemapper is
port(
	nrst, clk : in std_logic;
	rdata, idata : in std_logic_vector(5 downto 0);

	outbits : out std_logic_vector(1 downto 0));
end component;



component UpSample is
generic( UpRatio : integer := 4;
	 Dwidth  : integer := 6);
port(
	nrst, upclk : in std_logic;
	rdin, idin : in std_logic_vector((Dwidth-1) downto 0);

	rdout, idout : out std_logic_vector((Dwidth-1) downto 0));
end component;


component DnSample is
generic ( DnRatio : integer := 4;
	  Dwidth  : integer := 10;
	  LatchTime : integer := 7);
port(
	nrst, upclk, dnclk : in std_logic;
	rdin, idin : in std_logic_vector((Dwidth-1) downto 0);

	rdout, idout : out std_logic_vector((Dwidth-1) downto 0));
end component;




component psf17T is
port(
	nrst : in std_logic;
	clk : in std_logic;
	PSFin: in std_logic_vector(9 downto 0);
	PSFout : out std_logic_vector(9 downto 0));
end component;


component p2s is
generic(prate : in integer);
port(
	nrst, sclk : in std_logic;
	inbits : in std_logic_vector((prate-1) downto 0);

	outbit : out std_logic);
end component;

component UpConv_NCO is
port(
	nrst, clk : in std_logic;
	omega     : in std_logic_vector(7 downto 0);
	base_r, base_i : in std_logic_vector(9 downto 0);

	pass_r, pass_i : out std_logic_vector(9 downto 0));
end component;

component DnConv_NCO is
port(
	nrst, clk : in std_logic;
	omega : in std_logic_vector( 7 downto 0 );
	pass_r, pass_i : in std_logic_vector( 9 downto 0 );

	base_r, base_i : out std_logic_vector( 9 downto 0 ));
end component;

component PhaseSplitter is
port(
	nrst, clk : in std_logic;
	PS_Iin : in std_logic_vector(9 downto 0);

	PS_Iout, PS_Qout : out std_logic_vector(9 downto 0));
end component;


component DnConv_NCO_CR is
port(
	nrst, clk1x, clk4x : in std_logic;
	pass_r, pass_i : in std_logic_vector(9 downto 0);
	base_r1x, base_i1x : in std_logic_vector(9 downto 0);

	base_r, base_i : out std_logic_vector(9 downto 0));
end component;



signal nrst, mclk : std_logic;
signal clk8x, clk4x, clk2x, clk1x : std_logic;
signal rbit : std_logic;
signal s2pout : std_logic_vector(1 downto 0);
signal rmapout, imapout : std_logic_vector(5 downto 0);
signal rupout, iupout : std_logic_vector(5 downto 0);
signal rupout_0000, iupout_0000 : std_logic_vector(9 downto 0);
signal rpsfout1, ipsfout1 : std_logic_vector(9 downto 0);
signal rpassout, ipassout : std_logic_vector(9 downto 0);
signal rpsout, ipsout : std_logic_vector(9 downto 0);
signal rbaseout, ibaseout : std_logic_vector(9 downto 0);
signal rpsfout2, ipsfout2 : std_logic_vector(9 downto 0);

signal rdnout, idnout : std_logic_vector(9 downto 0);
signal rpsfout_final, ipsfout_final : std_logic_vector(5 downto 0);
signal rdmapin, idmapin : std_logic_vector(5 downto 0);
signal ri_after_demap : std_logic_vector(1 downto 0);
signal p2sout : std_logic;

begin

iclkgen : clkgen port map(
	nrst => nrst,
	mclk => mclk,
	clk8x => clk8x,
	clk4x => clk4x,
	clk2x => clk2x,
	clk1x => clk1x);

irbgen : rbgen port map(
	nrst => nrst,
	clk => clk4x,
	rbit => rbit);



is2p : s2p
generic map(prate => 2)
port map(
	nrst => nrst,
        sclk => clk4x,
	pclk => clk2x,
	inbit => rbit,
	outbits => s2pout);

iqmap : DQPSKmapper port map(
	nrst => nrst,
	clk => clk2x,
	cdata => s2pout,
	rout => rmapout,
	iout => imapout);


iupsam : UpSample
generic map(UpRatio => 4,
	    Dwidth  => 6)
port map(
	nrst => nrst,
	upclk => clk8x,
	rdin => rmapout,
	idin => imapout,

	rdout => rupout,
	idout => iupout);

rupout_0000 <= rupout & "0000";
iupout_0000 <= iupout & "0000";

ipsf17T_r_tx : psf17T port map(
	nrst => nrst,
	clk => clk8x,
	PSFin => rupout_0000,
	PSFout => rpsfout1);



ipsf17T_i_tx : psf17T port map(
	nrst => nrst,
	clk => clk8x,
	PSFin => iupout_0000,
	PSFout => ipsfout1);




iupconv : UpConv_NCO
port map(

	nrst => nrst,
	clk => clk8x,
	omega => "01000000",

	base_r => rpsfout1,
	base_i => ipsfout1,

	pass_r => rpassout,
	pass_i => ipassout);

iphasesplit : PhaseSplitter
port map(
	nrst => nrst,
	clk => clk8x,
	PS_Iin => rpassout,

	PS_Iout => rpsout,
	PS_Qout => ipsout);

idnconv : DnConv_NCO_CR
port map(

	nrst => nrst,
	clk1x => clk1x,
	clk4x => clk4x,

	pass_r => rpsout,
	pass_i => ipsout,
	base_r1x => rdnout,
	base_i1x => idnout,

	base_r => rbaseout,
	base_i => ibaseout);




ipsf17T_r_rx : psf17T port map(
	nrst => nrst,
	clk => clk8x,
	PSFin => rbaseout,
	PSFout => rpsfout2);

ipsf17T_i_rx : psf17T port map(
	nrst => nrst,
	clk => clk8x,
	PSFin => ibaseout,
	PSFout => ipsfout2);

idnsam : DnSample
generic map(DnRatio => 4,
	    Dwidth  => 10,
	    LatchTime => 2)
port map(
	nrst => nrst,
	upclk => clk8x,
	dnclk => clk2x,
	rdin => rpsfout2,
	idin => ipsfout2,

	rdout => rdnout,
	idout => idnout);

rdmapin <= rnd(rdnout, 4);
idmapin <= rnd(idnout, 4);


iqdemap : DQPSKdemapper
port map(
	nrst => nrst,
	clk => clk2x,
	rdata => rdmapin,
	idata => idmapin,

	outbits => ri_after_demap);

ip2s : p2s
generic map(prate => 2)
port map(
	nrst => nrst,
	sclk => clk4x,
	inbits => ri_after_demap,

	outbit => p2sout);
	

mclkp : process
begin
	mclk <= '1';
	wait for 20 ns;
	mclk <= '0';
	wait for 20 ns;
end process;


rstp : process
begin
	nrst <= '0';
	wait for 100 ns;
	nrst <= '1';
	wait;
end process;



end behavior;

---

Wave Capture