PhaseSpitter

RLT code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

library work;
use work.mypackage.all;

entity PhaseSplitter is
port(
	nrst, clk : in std_logic;
	PS_Iin : in std_logic_vector(9 downto 0);

	PS_Iout, PS_Qout : out std_logic_vector(9 downto 0));
end entity;

architecture arch of PhaseSplitter is

signal reg : std_10b_array(14 downto 0);
signal sub11b : std_11b_array(3 downto 0);
signal sum21b : std_21b_array(3 downto 0);
signal sum22b : std_22b_array(1 downto 0);
signal sum23b : std_logic_vector(22 downto 0);

constant hvector : std_10b_array(0 to 3) := std_10b_array'(

            conv_std_logic_vector(27,10),
            conv_std_logic_vector(45,10),
            conv_std_logic_vector(96,10),
            conv_std_logic_vector(321,10));

begin

process(nrst, clk)
begin

if nrst = '0' then
	reg <= (others => "0000000000");
	PS_Iout <= (others => '0');
	PS_Qout <= (others => '0');
elsif (clk'event and clk = '0' ) then
	reg(14 downto 1) <= reg(13 downto 0);
	reg(0) <= PS_Iin;
	PS_Iout <= reg(7);
	PS_Qout <= rndsat(sum23b, 9, 4);
	
end if;
end process;

stage0 : for i in 0 to 3 generate
	sub11b(i) <=  sxt(reg(14-2*i), 11) - sxt(reg(2*i), 11);
end generate;

stage1 : for i in 0 to 3 generate
	sum21b(i) <= sub11b(i) * hvector(i);
end generate;

stage2 : for i in 0 to 1 generate
	sum22b(i) <= sxt(sum21b(2*i), 22) + sxt(sum21b(2*i+1), 22);
end generate;

sum23b <= sxt(sum22b(0), 23) + sxt(sum22b(1), 23);

end arch;

---

TestBench code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;

entity tb_PhaseSpiltter is
end tb_PhaseSpiltter;

architecture behavior of tb_PhaseSpiltter is

component PhaseSplitter is
port(
	nrst, clk : in std_logic;
	PS_Iin : in std_logic_vector(9 downto 0);

	PS_Iout, PS_Qout : out std_logic_vector(9 downto 0));
end component;


signal nrst, clk : std_logic;
signal impulse, impout_i, impout_q : std_logic_vector(9 downto 0);


begin
iphasesplit : PhaseSplitter port map(
	nrst => nrst,
	clk => clk,
	PS_Iin => impulse,

	PS_Iout => impout_i,
	PS_Qout => impout_q);


clkp : process
begin
	clk <= '1';
	wait for 20 ns;
	clk <= '0';
	wait for 20 ns;
end process;

nrstp : process
begin
	nrst <= '0';
	wait for 100 ns;
	nrst <= '1';
	wait;
end process;

iimp : process
begin
	impulse <= "0000000000";
	wait for 140 ns;
	impulse <= "0111111111";
	wait for 40 ns;
	impulse <= "0000000000";
	wait;
end process;

end behavior;

---

Wave Capture