Up Conversion

RTL code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity upconv is
port(
	clk, nrst : in std_logic;
	base_r, base_i : in std_logic_vector(9 downto 0);
	
	pass_r, pass_i : out std_logic_vector(9 downto 0));
end entity;

architecture arch of upconv is

signal p_r, p_i, n_r, n_i : std_logic_vector(9 downto 0);
signal passing_r, passing_i     : std_logic_vector(9 downto 0);
signal state : std_logic_vector(1 downto 0);

begin

p_r <= base_r;
p_i <= base_i;
n_r <= not(base_r) + "0000000001";
n_i <= not(base_i) + "0000000001";


process(nrst,clk)
begin
if nrst = '0' then
	state <= "00";
elsif clk = '1' and clk'event then
	state <= state + "01";
end if;
end process;


process(nrst, clk)
begin
if nrst = '0' then
	passing_r <= "0000000000";
	passing_i <= "0000000000";
elsif clk = '1' and clk'event then
	if state = "00" then
		passing_r <= p_r;
		passing_i <= p_i;
	elsif state = "01" then
		passing_r <= n_i;
		passing_i <= p_r;
	elsif state = "10" then
		passing_r <= n_r;
		passing_i <= n_i;
	else
		passing_r <= p_i;
		passing_i <= n_r;
	end if;

end if;
end process;

pass_r <= passing_r;
pass_i <= passing_i;

end arch;

---

TestBench code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity tb_upconv is
end entity;

architecture behavior of tb_upconv is

component upconv is
port(
	clk, nrst : in std_logic;
	base_r, base_i : in std_logic_vector(9 downto 0);
	
	pass_r, pass_i : out std_logic_vector(9 downto 0));
end component;

signal nrst, clk : std_logic;
signal rin, iin : std_logic_vector(9 downto 0);
signal rout, iout : std_logic_vector(9 downto 0);

begin

iupconv : upconv port map(
	nrst => nrst,
	clk => clk,
	base_r => rin,
	base_i => iin,

	pass_r => rout,
	pass_i => iout);

clkp : process
begin
	clk <= '1';
	wait for 20 ns;
	clk <= '0';
	wait for 20 ns;
end process;

nrstp : process
begin
	nrst <= '0';
	wait for 100 ns;
	nrst <= '1';
	wait;
end process;

process(nrst, clk)
begin
if nrst = '0' then
	rin <= (others => '0');
	iin <= (others => '0');
elsif clk = '1' and clk'event then
	rin <= rin + '1';
	iin <= iin - '1';
end if;
end process;

end behavior;

---

Wave Capture